`timescale 1ns/1ps
module circuit3_top ;
    reg clk,D_in,reset;
    wire P_odd;
    always # 1 clk = ~clk;
    initial begin
        clk = 0;
        reset = 0;
        D_in = 0;
        # 1 reset = 1 ;
        # 3 reset = 0 ;
        # 3 D_in =1;
        # 10 D_in=0;
        # 8 D_in=1;
        # 2 reset = 0;
        # 2 $finish;
    end
    circuit3 c3(P_odd,D_in,clk,reset);
initial
	begin
    	$dumpfile("test.vcd");
    	$dumpvars(0, c3);
 	end
endmodule

module circuit3(P_odd,D_in,clk,reset);
	input D_in,clk,reset;
    output reg P_odd;
    always @ (posedge clk)
        if(reset)
            P_odd <= 0;
    	else
            P_odd <= D_in ^ P_odd;
endmodule
